The present invention relates to a spread spectrum communication and more particularly to a spread spectrum communication system conforming to a delayed multiplex mode transmission, and a method of communication using the system.
Spread spectrum communication systems have recently been developed, and have attracted a great deal of public attention as a new and interesting communication method. A typical modulation system used in conventional data communication systems is a narrow band modulation system which can be realized by relatively small circuitry, but which is weak to interference such as multipath interference and narrow band color noises. Such may occur indoors in offices and workplaces. On the contrary, the spread spectrum communication system is free from the above-mentioned problem since it can spread a data spectrum with a spread code and transmit the spread-spectrum coded data in a wide band.
The spread spectrum communication system, however, has a disadvantage of requiring a widened bandwidth to transmit data at a high speed. For example, a bandwidth of 22 MHz is required to realize spread-spectrum transmission of QPSK (Quadrature Phase Shift Keying) modulated data with 11 chips of spread code at a transmission rate of 2 Mbps. Namely, the bandwidth of 110 MHz is needed to transmit data at 10 Mbps. The fact that radio transmission has a restriction on bandwidth makes it more difficult to realize the high-speed data transmission by the spread-spectrum communication method.
Accordingly, a method for multiplexing spectrum signals with a delay (hereinafter called xe2x80x9cDelayed multiplex systemxe2x80x9d) has been proposed as a method of transmitting data within a limited bandwidth at a high speed, which is described in Japanese Patent Application No. 7-206159.
The use of this method can increase the data transmission rate within a limited bandwidth. For example, the data transmission rate 2 Mbps at 22 MHz (as described before) can be increased to 4 Mbps by multiplexing the data twice and further to 10 Mbps by multiplexing the data five times.
FIG. 6 shows a typical block diagram of a conventional system used for proposed delayed multiplex transmission method. In FIG. 6, data generated by a data generating section 10 is differentially coded by a differential coding section 11 and then converted to parallel sets of data to be multiplexed by a series-to-parallel (S/P) converting section 12. The parallel data sets are transferred to respective multiplying sections (13-1xcx9c13-5) whereby they are spread by multiplying by a PN code received from a PN generator 14. Then, the parallel data sets are delayed respectively by the delay elements (15-1xcx9c15-5).
The delayed parallel data sets are combined by a frequency combining section 17 to form multivalued digital signals which are then modulated with oscillation of an oscillator 18 by a modulator 17 and transmitted through a frequency converter 19 and a power amplifier 20.
The high-speed data transmission within the limited bandwidth is thus accomplished.
However, the delayed multiplex data transmission still encounters an increase in error rate from interference between multiplexed signals.
Accordingly, the inventor of the present application also proposed a method for improving the correlation and error rate for the delayed multiplex transmission (Japanese Patent Application No. 8-13963).
FIG. 7 shows a typical circuit diagram of a conventional delayed multiplex system by which improvement in error rate has been realized. This example is described below. The transmission system is the same with the system shown before in FIG. 6. In the receiving system of FIG. 7, a received frequency signal is converted to a base band signal by a frequency converting section 21 and correlated by a correlator 23. The correlation is latched by a latch section 24 at the timing of a correlating spike and, then, is recovered from the deterioration due to auto-correlation by a correlation processing section 25. This correlation output is distributed by a distributor 26. The signal is controlled by a latch controller 29 and latched by latch sections 27 and 28. According to the aforementioned actual example, the signal is latched with 2 chips or 3 chips.
The signal is differentiated by a differential section 30 and discriminated and demodulated by a discriminating section 31.
FIG. 8 is a typical construction block diagram of the correlating processing section of FIG. 7. This depicts a five-multiplex case. In FIG. 8, there is shown only one line that must be doubled for realizing the system of FIG. 7.
An input signal is input to shift registers 25S corresponding to the number of input bits. The registers hold correlation spikes by four before and after a desired demodulation timing spike. An arithmetic unit 25P with a selecting function carries-out operations on the signals at a timing signal generated by a timing signal generator 25T which matches the timings of input and output according to signals from a correlation synchronizing circuit (not shown in FIG. 8).
FIG. 9 is a block diagram showing a typical internal construction of the arithmetic unit with a selecting function, which is shown in FIG. 8.
The use of the unit of FIG. 9 can considerably decrease a change in amplitude of a signal due to the influence of an auto-correlation side-lobe, and can therefore make a great improvement in error rate. The operation of this unit is as follows:
As seen in FIG. 9, signals A and F are input to a selector 25P1, signals B and G are input to a selector 25P2, signals C and H are input to a selector 25P3 and signals D and I are input to a selector 25P4. In this instance, the selectors 25P1-25P4 select signals A, B, C and D respectively. The selected signals A-D are added together by an adder 25P5 and then divided by 11 by a divider 25P6. The resultant signal is added to Exe2x80x2 by an adder-subtracter 25P9, then latched by a latching section 25P8 and output.
In the example shown, preceding and proceeding correlation signals are used for improvement of the correlation output. When received signals are 5-multiplex signals, each signal is composed of five blocks and five correlatin outputs are used for improvement in correlation. However, five blocks cannot be obtained due to the transmitted data length.
FIG. 10 is a conceptual illustration of an exemplified state of five-multiple data. In the case shown, there is no data in the two last blocks (i.e., the two last symbols are lost) since these signals, (outputs of respective delay elements) before being multiplexed, do not have the data length of a multiple of 5. Consequently, data consisting of 128 symbols is divided into 5 groups, each consisting of 5 blocks of 5 symbols, and thus 3 symbols remain, as shown in FIG. 10. In this instance, the conventional correlation-improved circuit cannot exert a sufficient effect of improving the correlation because blocks of coded signals are partly omitted. Thus, an error rate for the last three symbols worsens. In packet communication, 1 bit error causes retransmission of data. Therefore, an increase in error rate for above-mentioned symbols decreases the throughput of the packet transmission system.
In view of the above-mentioned problems, the present invention was made to provide a direct spread spectrum communication system conforming to a delayed multiplex mode transmission and a communication method using the system, which can realize improvement in correlation and improvement in error rate in any data length by applying the above mentioned technical means featuring the present invention.
(1) In view of the above-mentioned problems, the present invention was made to provide a direct spread spectrum communication system conforming to a delayed multiplex mode transmission and a communication method using the system, which can realize improvement in correlation and improvement in error rate in any data length by applying the above mentioned technical means featuring the present invention.
(2) Another object of the present invention is a direct spread spectrum communication system conforming to a delayed multiplex mode as defined in above item (1), which is featured in that the system is further provided with means adapted for transmitting and receiving a simplex signal directly spread with a spread code.
(3) Another object of the present invention is to provide a direct spread spectrum communication system conforming to a delayed multiplex mode as defined in any of above items (1) and (2), which is featured in that the means are adapted to cause the number of additional bits to be an integer multiple of the multiplex number multiplied by the number of bits composing a unit to be processed by the system.
(4) Another object of the present invention is to provide a direct spread spectrum communication system conforming to a delayed multiplex mode for transmitting and receiving a plurality of series of signals directly spread by using a spread code and multiplexed by using multiplexing means for multiplexing signals at a delay time of any desired number of chip codes, which is further provided with means for appending an additional bit or bits before the start of a multiplex section following to a simplex section in a signal format for setting signals to be transmitted and received in a simplex mode and a multiplex mode.
(5) Another object of the present invention is to provide a communication method using any one of the direct spread spectrum communication systems mentioned above items (2) to (4) conforming to a delayed multiplex mode, which method is featured in that a length of additional bits to be inserted is set to a length corresponding to a transit period during which the operation of the system is unstable after switching the transmission mode from the simplex mode to the multiplex mode can be stabilized.
(6) Another object of the present invention is to provide a communication method, using any one of the direct spread spectrum communication systems mentioned above item (2) conforming to a delayed multiplex mode, which is featured in that an additional bit or bits having no relation to transmissive data are inserted before the start of a multiplex section following to a simplex section in a signal format for setting signals to be transmitted and received in a simplex mode and a multiplex mode.
(7) Another object of the present invention is to provide a communication method, using any one of the direct spread spectrum communication systems mentioned above items (5) and (6) conforming to a delayed multiplex mode, which is featured in that error correction such as convolutional coding in the multiplex section is applied to a format of data to be transmitted in the multiplex mode according to the signal format in such a way that the appendable additional bit or bits are given specific data according to the error correction scheme to use for training of error correction processing.
(8) Another object of the present invention is to provide a communication method, using any one of the direct spread spectrum communication systems mentioned above items (5) to (7) conforming to a delayed multiplex mode, which is characterized in that the system uses a specific data format that allows error checking such as CRC to be conducted on only the data omitting the additional bit or bits appended thereto.
(9) Another object of the present invention is to provide a communication method, using any one of the direct spread spectrum communication systems mentioned above items (5) to (8) conforming to a delayed multiplex mode, characterized in that the number of additional bits is an integer multiple of the multiplex number multiplied by the number of bits composing a unit to be processed by the system.
In the communication system according to the present invention, every packet may contain complete blocks with no omitted symbol, even in the last section thereof, by appending additional bits so as to form a packet consisting of, e.g., five blocks when the number of multiplexed signals is 5. This may solve the problem of increasing an error rate due to lack of or omission of a last symbol when multiplexing signals, which is required in prior art systems.
In the communication system for transmitting data having a simplex section and multiplex section, the transmission error rate of the whole system and the packet throughput of the system can be improved by selectively appending additional bits to the multiplex sections.
The additional bits interposed between a simplex section and a multiplexed section can prevent the transmit data from being affected by the unstable operations of digital and analog circuits during a transitional period after switching from a simplex section to a multiplexed section, consequently increasing the throughput of the communication system of the present invention. In detail, the additional bit section is placed between a simplex section and a multiplexed section in such a way that {circle around (1)} the number of the bits included the additional bit section corresponds to a time longer than that required for stabilizing the operation of the system (i.e., the length of transitional section plus the unstable section) and {circle around (2)} a total number of added symbols (bits) and symbols in the multiplexed section is an integer multiple of the multiplex number. The data format thus defined enables the additional bits to protect data against the influence of unstable period of the system and improve the transmission error rate of the system due to a lacking of a block.
The content of additional bits is controlled so as to cause the bits to function as the preprocessed section for convolutional coding of the data. Thus, the transmit data from the head (effective bit) can be effectively corrected for possible error in the format when conducting error correction with the convolutional codes.
CRC (Cyclic Redundancy Checking) can be conducted on only the effective data, omitting the additional bits and the calculation with the additional bits. This assures effective error detection and the improved throughput of the whole system.
The number of additional bits is selected to be equal to a common multiple of the multiplex number and a unit of bits (e.g., 8 bits) to be processed by the system, whereby the transmission length can be represented in a byte unit. Thus, calculation using fractions is not needed, thereby facilitating communication processing.